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ADNS-5030 low power optical mouse sensor data sheet description the avago technologies ADNS-5030 is a low power, small form factor optical mouse sensor. it has a new low-power architecture and automatic power management modes, making it ideal for battery, power-sensitive applications C such as cordless input devices. the ADNS-5030 is capable of high-speed motion detection C up to 14 ips and 2g. in addition, it has an on-chip oscillator and led driver to minimize external components. the ADNS-5030 along with the adns-5100/adns-5100- 001 lens, adns-5200 clip, and hlmp-ed80 led form a complete and compact mouse tracking system. there are no moving parts, which means high reliability and less maintenance for the end user. in addition, precision optical alignment is not required, facilitating high volume assembly. the sensor is programmed via registers through a four- wire serial port. it is housed in an 8-pin staggered dual in-line package (dip). theory of operation the ADNS-5030 is based on optical navigation technol - ogy, which measures changes in position by optically acquiring sequential surface images (frames) and math - ematically determining the direction and magnitude of movement. the ADNS-5030 contains an image acquisition system (ias), a digital signal processor (dsp), and a four wire serial port. the ias acquires microscopic surface images via the lens and illumination system. these images are processed by the dsp to determine the direction and distance of motion. the dsp calculates the d x and d y relative dis - placement values. an external microcontroller reads the d x and d y informa - tion from the sensor serial port. the microcontroller then translates the data into ps2, usb, or rf signals before sending them to the host pc. features ? low power architecture ? small form factor ? self-adjusting power-saving modes for prolonging battery life ? high speed motion detection up to 14 ips and 2 g ? self-adjusting frame rate for optimum performance ? internal oscillator C no clock input needed ? selectable 500 and 1000 cpi resolution ? operating voltage: 3.3 v nominal ? four wire serial port interface ? minimal number of passive components applications ? optical mice and optical trackballs ? integrated input devices ? battery-powered input devices
pinout of ADNS-5030 optical mouse sensor figure 1. package outline drawing (top view). pin name description 1 miso serial data output (master in/slave out) 2 xy_led led control 3 nreset reset pin (active low input) 4 ncs chip select (active low input) 5 sclk serial clock input 6 gnd ground 7 vdd3 supply voltage 8 mosi serial data input (master out/slave in) figure 2. package outline drawing. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. 4.32 (0.170) 9.10 (0.358) 12.85 0.45 (0.506 0.018) notes: 1. ? dimensions in millimeters (inches) . 2. ? dimensional tolerance: 0.1 mm. 3. ? coplanarity of leads: 0.1 mm. 4. ? cumulative pitch tolerance: 0.15 mm. 5. ? lead pitch tolerance: 0.15 mm. 6. ? maximum flash: + 0.2 mm. 7. ? lead width: 0.5 mm. 8. ? angular tolerance: 3.0 . (at lead tip) 12.85 (0.506) (at shoulder) 0.25 (0.010) pin 1 9.90 (0.390) 0.50 (0.020) lead width 1.00 (0.039) lead offset 2.00 (0.079) lead pitch 4.45 (0.175) 2.00 (0.079) pin 1 4.55 (0.179) 5.60 (0.220) (at base) ? 5.00 (0.197) protective kapton tape ? 0.80 (0.031) clear optical path ? 5.15 (0.203) 90 3 a5030 xyywwz a5030 xyywwz 5 sclk 6 gnd 7 vdd3 8 mosi 4 ncs 3 nreset 2 xy_led 1 miso
overview of optical mouse sensor assembly avago technologies provides an iges fle drawing de - scribing the base plate molding features for lens and pcb alignment. the ADNS-5030 sensor is designed for mounting on a through-hole pcb, looking down. there is an aperture stop and features on the package that align to the lens. the adns-5100/5100-001 lens provides optics for the imaging of the surface as well as illumination of the figure 3. recommended pcb mechanical cutouts and spacing. surface at the optimum angle. features on the lens align it to the sensor, base plate, and clip with the led. the adns-5200 clip holds the led in relation to the lens. the led must be inserted into the clip and the leds leads formed prior to loading on the pcb. the hlmp-ed80 led is recommended for illumination.
figure 4. 2d assembly drawing of ADNS-5030 (top and side view). 13.10 (0.516) 33.45 (1.317) base plate dimensions in mm (inches) 10.58 (0.417) 2.40 (0.094) 7.45 (0.293) top view cross section side view base plate sensor lens pcb top pcb to surface alignment post (optional) navigation surface led clip led bottom of lens flange to surface
figure 5. exploded view drawing. pcb assembly considerations 1. insert the sensor and all other electrical components into pcb. 2. insert the led into the assembly clip and bend the leads 90 degrees. 3. insert the led clip assembly into pcb. 4. wave solder the entire assembly in a no-wash solder process utilizing solder fxture. the solder fxture is needed to protect the sensor during the solder process. it also sets the correct sensor-to-pcb distance as the lead shoulders do not normally rest on the pcb surface. the fxture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. 5. place the lens onto the base plate. 6. remove the protective kapton tape from optical aperture of the sensor. care must be taken to keep contaminants from entering the aperture. recommend not to place the pcb facing up during the entire mouse assembly process. recommend to hold the pcb frst vertically for the kapton removal process. 7. insert pcb assembly over the lens onto the base plate aligning post to retain pcb assembly. the sensor aperture ring should self-align to the lens. 8. the optical position reference for the pcb is set by the base plate and lens. note that the pcb motion due to button presses must be minimized to maintain optical alignment. 9. install mouse top case. there must be a feature in the top case to press down onto the pcb assembly to ensure all components are interlocked to the correct vertical height. figure 6. block diagram of ADNS-5030 optical mouse sensor. power and control serial port and registers image array dsp oscillator led drive xy_led gnd vdd3 ncs ADNS-5030 sclk mosi miso nreset adns-5100 (lens) customer supplied pcb hlmp-ed80 (led) adns-5200 (led clip) sensor customer supplied base plate with recommended alignment features per iges drawing
design considerations for improved esd performance for improved electrostatic discharge performance, typical creepage and clearance distance are shown in the table below. assumption: base plate construction as per the avago technologies supplied iges fle and adns- 5100/5100-001 lens. typical distance millimeters creepage 16.0 clearance 2.1 note that the lens material is polycarbonate or polysty - rene hh30, therefore, cyanoacrylate based adhesives or other adhesives that may damage the lens should not be used. figure 7. sectional view of pcb assembly highlighting optical mouse components. lens/light pipe base plate surface sensor led clip pcb
figure 8. schematic diagram for interface between ADNS-5030 and microcontroller (cordless application). recommended typical application (transmitter side) recommended typical application (receiver side) 8 7 6 5 4 3 2 1 11 v in nsd c fil gnd gnd gnd gnd gnd v out c1+ c1 ? c2+ c2- c3+ c3 ? nc 10 13 15 9 12 14 16 adns-5100 lens surf ace 2 internal image sensor xy_led hlmp ed80 7 miso sclk nreset mosi ncs gnd v dd 6 1 5 3 8 4 0.1 f 100 f 0.33 f 15 f 1 f 0.33 f 0.33 f 40 pf 40 pf p3.3 p3.4 p3.5 p3.0 p3.1 p3.2 p1.5 p1.6 p1.7 p1.0 p1.1 p1.2 p1.3 p1.4 gnd gnd rst xt al2 xt al1 z led gnd v dd qa qb r l m buttons rf receiver circuitry rf transmitter circuitry 20 v cc v dd (3 v) v dd shld r2 2.7 ? 12 mhz r ? 6 mhz (optional) xt alout xt alin p0.5 p0.6 p0.7 v dd 0.1 f v dd (5 v) d+ d ? d+ d ? gnd shld 1.3 k ? v pp v reg mc u with usb features 3.0- vol t micro- controller lm3352 ADNS-5030 4.7 f 3.3 v recommended led bin: bin k and above (k, l, m, n, ...)
regulatory requirements ? passes fcc b and worldwide analogous emission limits when assembled into a mouse with shielded cable and following avago technologies recommendations. ? passes iec-1000-4-3 radiated susceptibility level when assembled into a mouse with shielded cable and following avago technologies recommendations. ? passes en61000-4-4/iec801-4 eft tests when assembled into a mouse with shielded cable and following avago technologies recom- mendations. ? ul fammability level ul94 v-0. ? provides sufcient esd creepage/clearance distance to avoid discharge up to 15 kv when assembled into a mouse using adns-5100 round lens according to usage instructions above. absolute maximum ratings parameter symbol minimum maximum units notes storage temperature t s -40 85 oc lead solder temperature 260 oc supply voltage v dd -0.5 3.7 v esd 2 kv all pins, human body model mil 883 method 3015 input voltage v in -0.5 v dd + 0.5 v all i/o pins output current iout 7 ma miso pin recommended operating conditions parameter symbol minimum typical maximum units notes operating temperature t a 0 40 oc power supply v dd 3.0 3.3 3.6 v power supply rise time v rt 0.005 100 ms 0 to v dd min supply noise (sinusoidal) v na 100 mvp-p 10 khz - 50 mhz serial port clock frequency f sclk 1 mhz 50% duty cycle distance from lens reference plane z 2.3 2.4 2.5 mm to tracking surface (z) speed s 0 14 ips acceleration a 2 g load capacitance c out 100 pf miso
ac electrical specifcations electrical characteristics over recommended operating conditions. typical values at 25 c, v dd = 3.3 v. parameter symbol minimum typical maximum units notes reset pulse width t reset 250 ns active low motion delay after reset t mot-rst 50 ms from nreset pull high to valid motion, assuming v dd and motion is present forced rest enable t rest-en 1 s from rest mode(rm) bits set to target rest mode wake from forced rest t rest-dis 1 s from rest mode(rm) bits cleared to valid motion power down t pd 50 ms from pd (when bit 1 of register 0x0d is set) to low current wake from power down t wakeup 50 55 ms from pd inactive (when nreset pin is asserted low to high or write 0x5a to register 0x3a) to valid motion miso rise time t r-miso 40 200 ns c l = 100 pf miso fall time t f-miso 40 200 ns c l = 100 pf miso delay after sclk t dly-miso 120 ns from sclk falling edge to miso data valid, no load conditions miso hold time t hold-miso 0.5 1/f sclk s data held until next falling sclk edge mosi hold time t hold-mosi 200 ns amount of time data is valid after sclk rising edge mosi setup time t setup-mosi 120 ns from data valid to sclk rising edge spi time between write t sww 30 s from rising sclk for last bit of the frst data byte, commands to rising sclk for last bit of the second data byte spi time between write and t swr 20 s from rising sclk for last bit of the frst data byte, read commands to rising sclk for last bit of the second address byte spi time between read t srw 250 ns from rising sclk for last bit of the frst data byte, to and subsequent commands t srr falling sclk for the frst bit of the next address spi read address-data t srad 4 s from rising sclk for last bit of the address byte, delay to falling sclk for frst bit of data being read ncs inactive after motion t bexit 250 ns minimum ncs inactive time after motion burst before burst next spi usage ncs to sclk active t ncs-sclk 120 ns from ncs falling edge to frst sclk rising edge sclk to ncs inactive t sclk-ncs 120 ns from last sclk rising edge to ncs rising edge, (for read operation) for valid miso data transfer sclk to ncs inactive t sclk-ncs 20 s from last sclk rising edge to ncs rising edge, (for write operation) for valid mosi data transfer ncs to miso high-z t ncs-miso 250 ns from ncs rising edge to miso high-z state transient supply current i ddt 60 ma max supply current during a v dd ramp from 0 to v dd figure 9. distance from lens reference plane to tracking surface (z). 2.40 (0.094) z = object surface sensor lens lens reference plane
10 figure 10. mean resolution vs. distance from lens reference plane to surface. typical performance characteristics (bit 0 of register 0x40 set to 0) figure 12. relative wavelength responsivity. figure 11. typical path deviation. dc electrical specifcations electrical characteristics over recommended operating conditions. typical values at 25c, v dd = 3.3 v. parameter symbol minimum typical maximum units notes dc supply current in various mode i dd_avg_high 15.2 17 ma average current, including led current, at max frame rate. no load on miso. bit 0 of register 0x40 set to 0 i dd_avg_low 11.3 13.1 ma average current, including led current, at max frame rate. no load on miso. bit 0 of register 0x40 set to 1 i dd_rest1 0.34 0.54 ma i dd_rest2 0.09 0.16 ma i dd_rest3 0.03 0.06 ma power down 2 ua input low voltage v il 0.5 v sclk, mosi, ncs, nreset input high voltage v ih v dd C 0.5 v sclk, mosi, ncs, nreset input hysteresis v i_hys 200 mv sclk, mosi, ncs, nreset input leakage current i leak 1 1 10 10 ma vin=vdd-0.6v, sclk, mosi, ncs, nreset output low voltage v ol 0.7 v iout=1ma, miso output high voltage v oh vdd -0.7 v iout=-1ma, miso input capacitance c in 50 pf mosi, ncs, sclk, nreset normalized response 400 0 wavelength (nm) 900 1.0 0.4 0.5 0.6 0.7 0.8 0.9 0.3 700 800 1000 0.1 0.2 600 500 0 200 400 600 800 1000 1200 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 distance from lens reference plane to tracking surface (z ) mean resolution (cpi ) white paper manila white melamine bookshelf black formica 0 5 10 15 20 25 30 35 40 45 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 distance from lens reference plane to tracking surface (z) maximun distance (mouse count) white pape r manila white melamine bookshelf black formica
11 power management modes the ADNS-5030 has three power-saving modes. each mode has a diferent motion detection period, afecting response time to mouse motion (response time). the sensor automatically changes to the appropriate mode, depending on the time since the last reported motion (downshift time). the parameters of each mode are shown in the following table. response time downshift time mode (typical) (typical) rest 1 14 ms <1s rest 2 68 ms 7 s rest 3 340 ms 410 s led mode for power savings, the led will not be continuously on. ADNS-5030 will pulse the led only when needed. synchronous serial port the synchronous serial port is used to set and read pa - rameters in the ADNS-5030, and to read out the motion information. the port is a four wire serial port. the host micro-control - ler always initiates communication; the ADNS-5030 never initiates data transfers. sclk, mosi, and ncs may be driven directly by a micro-controller. the port pins may be shared with other spi slave devices. when the ncs pin is high, the inputs are ignored and the output is tri-stated. the lines that comprise the spi port: sclk: clock input. it is always generated by the master (the micro-controller). mosi: input data. (master out/slave in) miso: output data. (master in/slave out) ncs: chip select input (active low). ncs needs to be low to activate the serial port; otherwise, miso will be high z, and mosi & sclk will be ignored. ncs can also be used to reset the serial port in case of an error. chip select operation the serial port is activated after ncs goes low. if ncs is raised during a transaction, the entire transaction is aborted and the serial port will be reset. this is true for all transactions. after a transaction is aborted, the normal address-to-data or transaction-to-transaction delay is still required before beginning the next transaction. to improve communication reliability, all serial transac - tions should be framed by ncs. in other words, the port should not remain enabled during periods of non-use because esd and eft/b events could be interpreted as serial communication and put the chip into an unknown state. in addition, ncs must be raised after each burst- mode transaction is complete to terminate burst-mode. the port is not available for further use until burst-mode is terminated. write operation write operation, defned as data going from the micro- controller to the ADNS-5030, is always initiated by the micro-controller and consists of two bytes. the frst byte contains the address (seven bits) and has a 1 as its msb to indicate data direction. the second byte contains the data. the ADNS-5030 reads mosi on rising edges of sclk. write operation 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 d 0 d 5 d 6 d 7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 1 a 6 d 4 d 3 d 2 d 1 sclk ncs mosi mosi driven by micro-controller miso
1 read operation a read operation, defned as data going from the adns- 5030 to the micro-controller, is always initiated by the micro-controller and consists of two bytes. the frst byte contains the address, is sent by the micro-controller over mosi, and has a 0 as its msb to indicate data direction. the second byte contains the data and is driven by the ADNS-5030 over miso. the sensor outputs miso bits on falling edges of sclk and samples mosi bits on every rising edge of sclk. read operation miso delay and hold time note: the 200 ns minimum high state of sclk is also the minimum miso data hold time of the ADNS-5030. since the falling edge of sclk is actually the start of the next read or write command, the ADNS-5030 will hold the state of data on miso until the falling edge of sclk. d 0 t hold-miso t dl y- miso sclk miso 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 0 a 1 a 2 a 3 a 4 a 5 a 6 sclk ncs sclk cycle # mosi d 0 d 5 d 6 d 7 t srad dela y d 4 d 3 d 2 d 1 miso mosi setup and hold time t setup, mosi t hold, mosi sclk mosi
1 required timing between read and write commands there are minimum timing requirements between read and write commands on the serial port. during a read operation sclk should be delayed at least t srad after the last address data bit to ensure that the ADNS-5030 has time to prepare the requested data. the falling edge of sclk for the frst address bit of either the read or write command must be at least t srr or t srw after the last sclk rising edge of the last data bit of the previous read operation. timing between read and either write or subsequent read commands if the rising edge of sclk for the last address bit of the read command occurs before the required delay (t swr ), the write command may not complete correctly. timing between write and read commands if the rising edge of the sclk for the last data bit of the second write command occurs before the required delay (t sww ), then the frst write command may not complete correctly. timing between two write commands sclk t sw w write operation address data write operation address data sclk t sw r write operation address data next read operation address ? ? ? ? ? ? sclk t srad read operation address next read or write operation address ? ? ? ? ? ? t srw & t srr data
1 burst mode operation burst mode is a special serial port operation mode that may be used to reduce the serial transaction time for a motion read. the speed improvement is achieved by continuous data clocking to or from multiple registers without the need to specify the register address, and by not requiring the normal delay period between data bytes. burst mode is activated by reading the motion_burst register. the ADNS-5030 will respond with the contents of the delta_x, delta_y, squal, shutter_upper, shutter_ lower, and maximum_pixel and pixel_sum registers in that order. the burst transaction can be terminated anywhere in the sequence after the delta_x value by bringing the ncs pin high. after sending the register address, the micro-controller must wait t srad and then begin reading data. all data bits can be read with no delay between bytes by driving sclk at the normal rate. the data are latched into the output bufer after the last address bit is received. after the burst transmission is complete, the micro-controller must raise the ncs line for at least t bexit to terminate burst mode. the serial port is not available for use until it is reset with ncs, even for a second burst transmission. avago technologies highly recommends the usage of burst mode operation in optical mouse sensor design applications. motion burst timing notes on power-up and reset the ADNS-5030 does not perform an internal power up self-reset; the nreset pin must be asserted low every time power is applied. there are two ways to reset the chip, either assert low nreset pin or by writing 0x5a to register 0x3a. a full reset will thus be executed. any register settings must then be reloaded. during power-up there will be a period of time after the power supply is high but before any clocks are available. the table below shows the state of the various pins during power-up and reset. state of signal pins after vdd is valid pin during reset after reset ncs ignored functional miso low depends on ncs sclk ignored depends on ncs mosi ignored depends on ncs xy_led high functional notes on power down the ADNS-5030 can be set in power down mode by setting bit 1 of register 0x0d. in addition, the spi port should not be accessed during power down. (other ics on the same spi bus can be accessed, as long as the sensors ncs pin is not asserted.) the table below shows the state of various pins during power down. there are 2 ways to exit power down, either assert low nreset pin or by writing 0x5a to register 0x3a. a full reset will thus be executed. wait t wakeup before accessing the spi port. any register settings must then be reloaded. pin power down active nreset functional ncs functional* miso undefned sclk functional* mosi functional* xy_led low current * ncs pin must be held to 1 (high) if spi bus is shared with other devices. it can be in either state if the sensor is the only device in addition to the controller microprocessor. note: there is long wakeup time from power down. this feature should not be used for power management during normal mouse motion. motion_burst register address read first byte first read operation read second byte read third byte sclk t srad
1 registers the ADNS-5030 registers are accessible via the serial port. the registers are used to read motion data and status as well as to set the device confguration. address register read/write default value 0x00 product_id r 0x11 0x01 revision_id r 0x00 0x02 motion r 0x00 0x03 delta_x r any 0x04 delta_y r any 0x05 squal r any 0x06 shutter_upper r any 0x07 shutter_lower r any 0x08 maximum_pixel r any 0x09 pixel_sum r any 0x0a minimum_pixel r any 0x0b pixel_grab r/w any 0x0c reserved 0x0d mouse control r/w 0x00 0x0e C 0x39 reserved 0x3a chip_reset w n/a 0x3b C 0x3e reserved 0x3f inv_rev_id r 0xf 0x40 sensor_current_setting w n/a 0x41 C 0x44 reserved 0x45 rest_mode_confguration r/w 0x00 0x46 C 0x62 reserved 0x63 motion_burst r 0x00
1 field name description mot motion since last report 0 = no motion 1 = motion occurred, data ready for reading in delta_x and delta_y registers reserved reserved motion address: 0x02 access: read/write reset value: 0x00 revision_id address: 0x01 access: read reset value: 0x00 product_id address: 0x00 access: read reset value: 0x11 data type: 8-bit unsigned integer usage: this register contains a unique identifcation assigned to the ADNS-5030. the value in this register does not change; it can be used to verify that the serial communications link is functional. bit 7 6 5 4 3 2 1 0 field pid 7 pid 6 pid 5 pid 4 pid 3 pid 2 pid 1 pid 0 data type: 8-bit unsigned integer usage: this register contains the ic revision. it is subject to change when new ic versions are released. bit 7 6 5 4 3 2 1 0 field rid 7 rid 6 rid 5 rid 4 rid 3 rid 2 rid 1 rid 0 data type: bit feld usage: register 0x02 allows the user to determine if motion has occurred since the last time it was read. if the mot bit is set, then the user should read registers 0x03 and 0x04 to get the accumulated motion. read this register before reading the delta_x and delta_y registers. writing anything to this register clears the mot bit, delta_x and delta_y registers. the written data byte is not saved. bit 7 6 5 4 3 2 1 0 field mot reserved reserved reserved reserved reserved reserved reserved
1 delta x address: 0x03 access: read reset value: 0x00 data type: eight bit 2s complement number usage: x movement is counts since last report. absolute value is determined by resolution. reading clears the register. note: avago technologies recommends that registers 0x03 and 0x04 be read sequentially. bit 7 6 5 4 3 2 1 0 field x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 delta_y address: 0x04 access: read reset value: 0x00 data type: eight bit 2s complement number usage: y movement is counts since last report. absolute value is determined by resolution. reading clears the register. note: avago technologies recommends that registers 0x03 and 0x04 be read sequentially. bit 7 6 5 4 3 2 1 0 field y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 80 81 fe ff 00 01 02 7e 7f -128 -127 -2 -1 0 + 1 + 2 +126 +127 motion del t a_x 80 81 fe ff 00 01 02 7e 7f -128 -127 -2 -1 0 + 1 + 2 +126 +127 motion del t a_y
1 squal address: 0x05 access: read reset value: 0x00 figure 13. squal values (white paper). figure 14. mean squal vs. z (white paper). data type: upper 8 bits of a 9-bit unsigned integer usage: squal (surface quality) is a measure of the number of valid features visible by the sensor in the current frame. the maximum squal register value is 144. since small changes in the current frame can result in changes in squal, variations in squal when looking at a surface are expected. the graph below shows 250 sequentially acquired squal values, while a sensor was moved slowly over white paper. squal is nearly equal to zero, if there is no surface below the sensor. squal is typically maximized when the navigation surface is at the optimum distance from the imaging lens (the nominal z- height). bit 7 6 5 4 3 2 1 0 field sq 7 sq 6 sq 5 sq 4 sq 3 sq 2 sq 1 sq 0 squal (white paper) 0 10 20 30 40 50 60 70 80 90 100 1 101 201 301 401 501 601 701 801 count squal value mean squal vs z (white paper) -10 0 10 20 30 40 50 60 70 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 delta from nominal focus (mm) squal value (count) avg-3sigma avg avg+3sigma
1 shutter_upper address: 0x06 access: read reset value: 0x00 data type: sixteen bit unsigned integer usage: units are clock cycles. read shutter_upper frst, then shutter_lower. they should be read con - secutively. the shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. the shutter value is automatically adjusted. bit 7 6 5 4 3 2 1 0 field s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 bit 7 6 5 4 3 2 1 0 field s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 shutter_lower address: 0x07 access: read reset value: 0x00 figure 15. shutter (white paper). figure 16. mean shutter vs. z (white paper). shutter (white paper) shutter value 0 50 100 150 200 250 300 1 101 201 301 401 501 601 701 801 count 0 50 100 150 200 250 300 350 400 450 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 distance from lens reference plane to tracking surface (z) mean shutter value (count) avg-3sigm a av g avg+3sigma
0 data type: eight-bit number usage: maximum pixel value in current frame. minimum value = 0, maximum value = 127. the maximum pixel value can vary with every frame. bit 7 6 5 4 3 2 1 0 field mp 0 mp 6 mp 5 mp 4 mp 3 mp 2 mp 1 mp 0 maximum_pixel address: 0x08 access: read reset value: 0x00 pixel_sum address: 0x09 access: read reset value: 0x00 data type: high 8 bits of an unsigned 15-bit integer usage: this register is the accumulated pixel value from the last image taken. the maximum accumulator value is 28,575, but only bits [14:7] are reported. it may be described as the full sum divided by 1.76. the maximum register value is 223. the minimum is 0. the pixel sum value can change on every frame. bit 7 6 5 4 3 2 1 0 field ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 data type: eight-bit number usage: minimum pixel value in current frame. minimum value = 0, maximum value = 127. the minimum pixel value can vary with every frame. bit 7 6 5 4 3 2 1 0 field mp 0 mp 6 mp 5 mp 4 mp 3 mp 2 mp 1 mp 0 minimum_pixel address: 0x0a access: read reset value: 0x00
1 pixel_grab address: 0x0b access: read/write reset value: 0x00 data type: eight-bit word usage: the pixel grabber captures 1 pixel per frame. if there is a valid pixel in the grabber when this register is read, the msb will be set, an internal counter will incremented to capture the next pixel and the grabber will be armed to capture the next pixel. it will take 225 reads to upload the complete image. any write to this register will reset and arm the grabber to grab pixel 0 on the next image. bit 7 6 5 4 3 2 1 0 field valid pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 physical pixel address map C readout order of the array (looking through the sensor aperture at the bottom of the package) top x-ray view of mouse rb lb positive x positive y last pixel 224 209 194 179 164 149 134 119 104 89 74 59 44 29 14 223 208 193 178 163 148 133 118 103 88 73 58 43 28 13 222 207 192 177 162 147 132 117 102 87 72 57 42 27 12 221 206 191 176 161 146 131 116 101 86 71 56 41 26 11 220 205 190 175 160 145 130 115 100 85 70 55 40 25 10 219 204 189 174 159 144 129 114 99 84 6 9 5 4 3 9 2 4 9 218 203 188 173 158 143 128 113 98 83 6 8 5 3 3 8 2 3 8 217 202 187 172 157 142 127 112 97 82 6 7 5 2 3 7 2 2 7 216 201 186 171 156 141 126 111 96 81 66 51 36 21 6 215 200 185 170 155 140 125 110 95 80 6 5 5 0 3 5 2 0 5 214 199 184 169 154 139 124 109 94 79 6 4 4 9 3 4 1 9 4 213 198 183 168 153 138 123 108 93 78 6 3 4 8 3 3 1 8 3 212 197 182 167 152 137 122 107 92 77 6 2 4 7 3 2 1 7 2 211 196 181 166 151 136 121 106 91 76 6 1 4 6 31 16 1 first 210 195 180 165 150 135 120 105 90 75 6 0 4 5 3 0 1 5 0 pixel positive x positive y bottom view of mouse hole at mouse bottom cover for lens
mouse_control address: 0x0d access: read/write reset value: 0x00 data type: eight bit number usage: mouse sensor resolution and power down settings can be accessed or to be edited by this register. field name description pd power down 0 = normal 1 = power down res set resolution 0 = 500 cpi 1 = 1000 cpi reserved reserved reserved address: 0x0c reserved address: 0x0e-0x39 chip_reset address: 0x3a access: write reset value: 0x00 bit 7 6 5 4 3 2 1 0 field reserved reserved reserved reserved reserved reserved pd res data type: 8-bit unsigned integer usage: write 0x5a to initiate chip reset. bit 7 6 5 4 3 2 1 0 field cr 7 cr 6 cr 5 cr 4 cr 3 cr 2 cr 1 cr 0 inv_rev_id address: 0x3f access: read reset value: 0xf reserved address: 0x3b-0x3e data type: inverse 8-bit unsigned integer usage: this register contains the inverse of the revision id which is located at register 0x01. bit 7 6 5 4 3 2 1 0 field rrid 7 rrid 6 rrid 5 rrid 4 rrid 3 rrid 2 rrid 1 rrid 0
reserved address: 0x41-0x44 rest_mode_confguration address: 0x45 access: read/write reset value: 0x00 data type: bit feld usage: register 0x45 allows the user to change or monitor the rest mode confguration of the sensor. write operations to rm 1 and rm 0 forces the sensor into rest mode. read rm 1 and rm 0 for the sensor to report which mode it is in. note: forced rest has a long wakeup time and should not be used for power management during normal mouse motion. bit 7 6 5 4 3 2 1 0 field rm 1 rm 0 reserved reserved reserved reserved reserved reserved sensor_current_setting address: 0x40 access: write reset value: n/a data type: 8-bit number usage: this register is used to set the internal led drivers drive strength. bit 7 6 5 4 3 2 1 0 field reserved reserved reserved reserved reserved reserved reserved ldc field name description ldc internal led driver current 0 = high current 1 = low current reserved reserved field name description rm [1-0] write operation: force rest mode selection 00 = normal operation 01 = rest1 10 = rest2 11 = rest3 rm [1-0] read operation: reports which mode the sensor is in. 00 = run 01 = rest1 10 = rest2 11 = rest3 reserved reserved
for product information and a complete list of distributors, go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. obsoletes av01-0096en av02-0113en - july 30, 2007 motion_burst address: 0x63 access: read reset value: 0x00 data type: various usage: read from this register to activate burst mode. the sensor will return the data in the delta_x, delta_y, squal, shutter_upper, shutter_lower, maximum_pixel and pixel_sum. if the burst is not terminated at this point, the internal address counter stops incrementing and pixel sum registers value will be continuously returned. bursts are terminated when ncs is raised. bit 7 6 5 4 3 2 1 0 field mb 7 mb 6 mb 5 mb 4 mb 3 mb 2 mb 1 mb 0 reserved address: 0x46-0x62

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